1. Field of the Invention
This invention relates to a memory control unit which controls memory access, and particularly to a memory control unit which is incorporated in a microprocessor system development support apparatus and is capable of changing the number of wait states and thus memory access time in accordance with memory performance.
2. Description of Related Art
A microprocessor system development support apparatus comprises components such as a central processing unit (CPU), a memory, a memory control unit and an input/output (I/O) interface; each component interconnected through a system bus. A microprocessor system development support apparatus carries out data input/output with the outside by controlling input and output devices via the I/O interface.
FIG. 1 shows a block diagram illustrating a microprocessor system development support apparatus using a conventional memory control unit. In the drawing, reference numeral 1 represents a CPU operating at a rate of an input clock CLK. CPU 1 accesses external input and output devices via two read only memories (ROMs) 4a, 4b, and a random access memory (RAM) 5 which are arranged on a circuit board and an I/O interface not shown in the drawing, by means of an address bus ADB and a data bus DTB. The CPU 1 outputs address signals to the address bus ADB and carries out input and output of data via the data bus DTB. The CPU 1 also outputs an address enable signal AS which indicates that an effective address signal AD is outputted over the address bus ADB, and a data enable signal DS which indicates that data DA on the data bus DTB is effective, to a chip selector 2 which selects the ROM 4a, 4b, or RAM 5. The CPU 1 further outputs a read/write signal RD/WR which indicates whether the operation is reading or writing, to one input of an OR gate 8 and to one input of an OR gate 7 through an inverter 6. Other inputs of OR gates 7 and 8 receive the data enable signal DS from the CPU 1. The output from the OR gate 7 is fed to terminals OE of the ROM 4a and ROM 4b, and the output from the OR gate 8 is fed to a terminal WR of RAM 5. The chip selector 2 is also provided with the address signal AD from the address bus ADB, and thereby determines which memory to access, ROM 4a, 4b, or RAM 5, and accordingly asserts one of three chip selection signals ROM4a-SEL, ROM4b-SEL and RAM5-SEL which are output to the selector terminals CS of ROM 4a, 4b, and RAM 5, respectively and to a memory control unit 3 to be described later.
FIG. 2 shows a block diagram illustrating the primary elements of the conventional memory control unit 3. The memory control unit 3 has three shift registers 10a, 10b, 10c and inverters 11a, 11b, 11c corresponding to the memory units 4a, 4b, 5, respectively, as well as an inverter 13. A bus clock signal BCLK supplied by a clock generator (not shown in the drawing of the memory control unit 3) is outputted to the shift registers 10a, 10b, 10c. The shift registers 10a, 10b, 10c receive the chip selection signals ROM4a-SEL, ROM4b-SEL and RAM5-SEL which select memory units 4a, 4b, 5 via the inverters 11a, 11b, 11c, respectively. The shift registers 10a, 10b, 10c, are 8-bit registers giving output signals which have been shifted at every bus cycle, from the output terminals D1, D2, . . . D8. Now assuming that reading of the ROM 4a requires a wait time of 2 bus cycles, reading of the ROM 4b requires 3 bus cycles, and reading and writing of the RAM 5 require 1 bus cycle, the output terminal D3 of the shift register 10a, D4 of the shift register 10b and D2 of the shift register 10c are selected (as described in more detail below) by jumper wires 12a, 12b, 12c, respectively, with the outputs being outputted to the CPU 1 via the inverter 13 as a response signal DC. Thus, the response signal DC which is delayed in accordance with the access characteristics of the memory units 4a, 4b, and 5 can be obtained.
Now the wait time required for reading and writing data will be explained. When designing a system utilizing a microprocessor, particularly a microprocessor system development support apparatus, it is necessary to examine whether the access timing of the memory being used complies with the timing of the signals in CPU 1. Because input and output of signals are carried out regularly in the CPU 1 in accordance with the reference clock signal (bus clock), reading and writing of data from and into the memory must be done within this specified interval. If reading and writing of data cannot be done within this period, a wait state during which no operation is performed for a predetermined period of time must be inserted.
FIG. 3 shows a timing chart explaining the address access time and data access time during data reading operation. To read data, the address access time tsu (DA-AD) from the output of address signal AD to the output of data signal DA must satisfy the condition denoted by the following equation (1), and the data access time tsu (DA-RS) from the output of signal RS to the output of data signal DA must satisfy the condition denoted by equation (2), as follows: EQU t.sub.su (DA-AD)&lt;(3+n)t.sub.c -t.sub.su.sup.1 -t.sub.su 2 (1) EQU t.sub.su (DA-RS)&lt;(2+n)t.sub.c -t.sub.su 2-t.sub.su.sup.3 ( 2)
where tc: bus cycle,
n: wait number (wait time/tc),
t.sub.su 1: time from output of address signal AD to its assertion,
t.sub.su 2: time from output of signal RS to its assertion,
tsu3: time from output of data signal DA to its assertion.
Consequently, as shown in FIG. 3, wait states need not be inserted when the address access time tsu (DA-AD) and the data access time tsu (DA-RS) for the memory are less than the value of the right sides of the equations (1) and (2) under the condition of n=0, respectively, although wait state(s) of wait number n must be inserted when the values of tsu are greater than these values.
FIG. 4 shows a timing chart explaining the data set-up time, address set-up time and the pulse duration of the write signal during a writing operation. When writing data, data set-up time td (DA-WS), from data output to negation of signal WS must satisfy the condition represented by equation (3); address set-up time ta (AD-CONT) from the output of the address to the assertion of the address must satisfy the condition represented by equation (4), and the pulse width tw (CONT) of the signal WS must satisfy the condition represented by equation (5), as follows: EQU t.sub.d (DA-WS)&lt;(2+n)t.sub.c ( 3) EQU t.sub.a (AD-CONT)&lt;t.sub.c -t.sub.su 4 (4) EQU t.sub.w (CONT)&lt;(2+n)t.sub.c -t.sub.su 4 (5)
where t.sub.su 4: period from writing of data to stabilization thereof.
Because the periods of time t.sub.su (DA-AD), t.sub.su (DA-RS), t.sub.d (DA-WS), t.sub.a (AD-CONT) and t.sub.w (CONT) on the left-hand side of equations (1) through (5) are determined by the access characteristics of the selected memory, wait number n must be determined so that the conditions represented by equations (1) through (5) are satisfied.
For this reason, output terminals D1, D2, . . . D8 of the shift registers 10a, 10b, 10c are selected by means of jumper wires 12a, 12b, 12c in accordance with the access characteristics, such as an anticipated access delay time, of memory units 4a, 4b, 5 in the memory control unit 3 to determine the wait number n in advance.
Now a data access operation of a microprocessor system development support apparatus using the conventional memory control unit 3 will be explained. FIG. 5 shows a flow chart explaining the data access operation. When address signal AD is outputted to the address bus ADB (step #1), the chip selector 2 reads the address signal AD, checks to see which memory unit is selected (step #2), and outputs the chip selection signal to the selected memory unit. The memory control unit 3 checks to see which memory unit is selected based on the chip selection signal. The memory control unit 3 determines (i.e., "sets") the wait number for use with the CPU 1 from the time taken by the selected memory unit to output the data in the case of a data read operation, and to write data in the case of a data write operation, to change the timing of outputting a response signal DC to the CPU 1 (step #3). Upon output of the response signal DC, the CPU 1 reads data from the data bus DTB or writes the data into the memory and accesses the memory (step #4), thereby ending the operation.
Now an operation of reading data from the memory will be explained with reference to the reading timing chart shown in FIG. 6. Clock C1 is an internal clock corresponding to the input clock CLK when the bus clock BCLK in the CPU 1 is in the state of "H" and clock C2 is an internal clock corresponding to the input clock CLK when the bus clock BCLK is in the state of "L". The CPU 1 operates these as internal clocks. RD/WR is a read/write signal which indicates the read/write state of the transmitted data, the "H" state thereof indicating data read operation. STATE represents the bus state of the CPU 1.
At the rise of clock C1 at state S1, address signal AD is outputted to the address bus ADB. The read/write signal RD/WR at this point is in the state of "H", indicating the read cycle. At the fall of the clock C1, address enable signal AS is asserted, indicating that an effective address signal AD is outputted to the address bus ADB and, at the same time, the chip selector 2 outputs a chip selection signal to the selected memory unit. The memory control unit 3 asserts the response signal DC at the rise of clock C1 at state S2, and the memory outputs data to the data bus DTB. In the CPU 1, the response signal DC is recognized at the fall of clock C2 at state S2, and data is taken into an input latch (not shown in the drawing) at the fall of clock C2 at state S2 to complete the read cycle. When the response signal DC is not asserted, the CPU 1 enters a wait state, and a wait state Sw of 1 bus cycle is inserted.
Now the reading operation from each memory unit will be explained.
An operation in which the RAM 5 is selected will be explained first.
Address signal AD is outputted to the address bus ADB at the rise of clock C1 at state S1. The chip selector 2 asserts the chip selection signal RAM5-SEL at the fall of clock C1 at state S1. The memory control unit 3 sets the wait number to 1 by means of the shift register 10c, which receives the input of the chip selection signal RAM5-SEL, and counts a wait cycle of 1 bus cycle. New signals are never generated in wait state Sw. The memory control unit 3 asserts the response signal DC at the rise of clock C1 at state S2. When the response signal DC is asserted, the RAM 5 decodes the address signal AD and the chip selection signal RAM5-SEL to recognize that it is selected and outputs data signal DA to the data bus DTB. When the response signal DC is asserted, the CPU 1 takes the data signal DA into the input latch at the rise of clock C2 at state S2.
Now an operation in which ROM 4a is selected will be explained. When the chip selector 2 selects the ROM 4a by means of the address signal AD, the memory control unit 3 sets the wait number to 2 by means of the shift register 10a, which received the chip selection signal ROM4a-SEL, and counts a wait cycle of 2 bus cycles. The CPU 1 then receives the data in the input latch at the fall of clock C2 at state S2.
When the RAM 5 is selected, the memory control unit 3 sets the wait number to 1 and counts a wait cycle of 1 bus cycle. The CPU 1 then takes in the data at the fall of clock C2 at state S2.
Now an operation of writing data into the RAM 5 will be explained in detail.
FIG. 7 is a timing chart of a writing operation. Data is outputted to the address bus ADB at the rise of clock C1 at state S1. The read/write signal RD/WR enters "L" state, indicating a write cycle. When the address enable signal AS is asserted and an effective address signal AD is on the address bus ADB at the fall of clock C1, the chip selector 2 recognizes that the RAM 5 is selected by means of the address signal AD and outputs a chip selection signal RAM5-SEL. The RAM 5 decodes the chip selection signal RAM5-SEL and the address signal AD and recognizes that it is not selected. The CPU 1, on the other hand, outputs data to the data bus DTB during state S1. At the fall of clock C2 at state S1, the data enable signal DS is asserted, indicating that the data bus DTB has settled. The RAM 5 takes in the data on the data bus DTB by logically ORing the read/write signal RD/WR and the data enable signal DS. Wait number 1 is inserted by means of the chip selection signal RAM5-SEL, which has been outputted to the shift register 10c of the memory control unit 3. The RAM 5 then stores the data and the response signal DC is outputted to the CPU 1. The response signal DC is checked at the fall of clock C2 at state S2 and, when the response signal DC is asserted, the data enable signal DS is negated to complete the write cycle. Now the CPU 1 enters a wait state until the response signal DC is asserted, and a wait state Sw of 1 bus cycle is inserted so that no new signals are generated.
Microprocessor system development support apparatuses are often operated by changing memory, particularly ROM. When a conventional memory control unit is used, a memory change requires a modification of the hardware, such as changing the jumper wires, because the wait number is fixed, resulting in a different operating speed and making it difficult to accommodate various memory devices of different wait numbers or states.